Logical Effort Delay Modeling of Sense Amplifier Based Charge Recycling Threshold Logic Gates

In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon, with improved performance and power dissipation compared to conventional logic. In this work, the problem of estimating the delay of circuits based on the Charge Recycling Threshold Logic (CRTL) gate implementation is addressed. A delay model is developed based on the recently proposed theory of Logical Effort. The model allows evaluation and comparison of high speed designs implemented in CRTL and conventional logic, The model is applied to the design of the 4-bit block carry-generate function and wide AND gates.